Since all reads and writes must be both 32-bits and aligned to work on all implementations, the two lowest bits of CONFIG_ADDRESS must always be zero, with the remaining six bits allowing you to choose each of the 64 32-bit words. The least significant byte selects the offset into the 256-byte configuration space available through this method. Bits 10 through 8 choose a specific function in a device (if the device supports multiple functions).
Bits 15 through 11 select the specific device on the PCI Bus.
Bits 23 through 16 allow the configuration software to choose a specific PCI bus in the system. Bit 31 is an enable flag for determining when accesses to CONFIG_DATA should be translated to configuration cycles. The CONFIG_ADDRESS is a 32-bit register with the format shown in following figure. CONFIG_ADDRESS specifies the configuration address that is required to be accesses, while accesses to CONFIG_DATA will actually generate the configuration access and will transfer the data to or from the CONFIG_DATA register. Two 32-bit I/O locations are used, the first location ( 0xCF8) is named CONFIG_ADDRESS, and the second ( 0xCFC) is called CONFIG_DATA. Only configuration mechanism #1 will be described here, as it is the only access mechanism that will be used in the future. Configuration mechanism #1 is the preferred method, while mechanism #2 is provided for backwards compatibility. Two distinct mechanisms are defined to allow the software to generate the required configuration accesses. This task is usually performed by the Host to PCI Bridge (Host Bridge). Systems must provide a mechanism that allows access to the PCI configuration space, as most CPUs do not have any such mechanism. This requires a big-endian processor, such as a Power PC, to perform the proper byte-swapping of data read from or written to the PCI device, including any accesses to the Configuration Address Space. PCI devices are inherently little-endian, meaning all multiple byte fields have the least significant values at the lower addresses. During the address phase of the configuration cycle, the processor can address one of 64 32-bit registers within the configuration space by placing the required register number on address lines 2 through 7 (AD) and the byte enable lines. The IDSEL acts as the classic "chip select" signal. A target is selected during a configuration access when its IDSEL signal is asserted. All PCI devices, except host bus bridges, are required to provide 256 bytes of configuration registers for this purpose.Ĭonfiguration read/write cycles are used to access the Configuration Space of each target device. The PCI specification provides for totally software driven initialization and configuration of each device (or target) on the PCI Bus via a separate Configuration Address Space. (Remember when counting the number of loads on the bus, a connector counts as one load and the PCI device counts as another, and sometimes two.) A single PCI bus can drive a maximum of 10 loads. The disadvantage of the PCI bus is the limited number of electrical loads it can drive. The PCI bus component and add-in card interface is processor independent, enabling an efficient transition to future processors, as well as use with multiple processor architectures.
By combining a transparent upgrade path from 132 MB/s (32-bit at 33 MHz) to 528 MB/s (64-bit at 66 MHz) and both 5 volt and 3.3 volt signalling environments, the PCI bus meets the needs of both low end desktop systems and high-end LAN servers. The PCI ( Peripheral Component Interconnect) bus was defined to establish a high performance and low cost local bus that would remain through several generations of products.